1. Field of the Invention
This invention relates to accessing data memories.
2. Description of the Prior Art
It is known to use a cache memory to improve the performance of a central processing unit (CPU) in a data processing system. A cache memory is a relatively small, high speed random access memory (RAM) which is used to store data which are frequently required by the CPU. Typically, the cache RAM is directly accessed by the CPU (rather than via, for example, an external memory management unit (MMU)) and is situated physically close to the CPU in order to reduce the signal propagation time between the CPU and the cache memory. These features mean that data can be stored in or retrieved from the cache RAM very quickly.
Cache RAMs are commonly organised as a number of cache "lines", where each line may store, say, eight data words. When the cache RAM is accessed, a whole line of data is read and placed onto output bit lines. If the next cache RAM access requires a data word from the same cache line, then there is no need to re-read that line; the word can simply be read from the output bit lines.
The operation of reading cache lines onto the output bit lines consumes a considerable proportion of the total power requirement of the cache RAM. This is because the reading operation involves precharging sense amplifiers to read the data, followed by charging of the highly capacitive bit lines themselves.
In one known type of cache RAM architecture, a single cache RAM is used to store both data words and processor instruction words. This can lead to a particularly high power consumption in cases where executing an instruction loaded from one cache line causes the processor to load data from or store data to a different cache line. In this situation, the processor initially loads an instruction from the cache RAM by causing the cache line storing that instruction to be read onto the bit lines. When the instruction is executed, the processor reads or writes to another cache line. This means that the cache line containing the instruction is discarded from the bit lines and the new cache line read onto the bit lines. (In the case of the processor writing to the cache RAM, the bit lines are used in the writing process and so the values currently held on the bit lines still have to be discarded). After the load of store operation has been completed, the new values held on the bit lines again have to be discarded and the original cache line re-read to allow the processor to access subsequent required instructions.
These multiple instruction-data-instruction accesses can increase considerably the power consumption and access time of the cache RAM. The increase in power consumption has been estimated as between 10 to 30% of the total cache power consumption; this can be a major problem with cache RAMs, which already use a relatively high proportion of system power. Also, as mentioned above, an increase in access time is particularly disadvantageous in a cache RAM, where a primary requirement is one of high speed operation.
It is an object of the invention to reduce the power consumption and access time of data memories, and in particular of cache memories. This object is especially relevant to data memories intended for use in portable, battery-powered equipment.